• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    A stack memory device which comprises a memory stack of n-bit registers with gating circuiting controlled by code inverters to allow first in - first out, first in - last out, last in - first out and other selective transfers of data within the stack.
    公开号:SU1026164A1
    申请号:SU797770872
    申请日:1979-10-19
    公开日:1983-06-30
    发明作者:Георгиев Дановски Людмил；Кирилов Касабов Никола
    申请人:Вмеи "Ленин" (Инопредприятие)；
    IPC主号:
    专利说明:

    The invention relates to a magazine storage device, which is used to temporarily store data, about which digital computers can work, which can be stored in Mm-digit numbers and which can be used in large, small and micro-digital computers. The known store (cell) register memory, which is used in the construction of some processes of computers / and consists of VJ on VI-bit registers connected in series from first to last and back through gates for paraphase-connection of registers elements N, the valve enable inputs are connected to control buses to transfer the contents of the registers from the first to the last, to duplicate the contents of the first register in the second and to exchange the contents of the first and second o register ipob. .. A disadvantage of store memory is the inability to rewrite already processed data without disturbing the order of data in the memory and the inability to randomly exchange data between device registers and not to output data from it. The known store memory is implemented in a conventional memory, which consists of a pointer of the current store memory cell and memory cells. The disadvantages of the store memory, besides those already mentioned, are lower speed associated with the need to read and write to or from the memory, as well as the occupation of a certain amount of memory when the store memory is part of the DSP processor device. the invention is the creation of a mass storage device that preserves the structural simplicity of the magazine memory and its ability to shift the contents of the registers Vpere duplication of the first register and volume between the first and second registers during the transfer Forward and the last register for the further storage of the possibility of any exchange between registers in the device when a particular control sequence is fed at its input. The goal is achieved by the fact that a magazine storage device consisting of ISC-discharge registers and gates for a pair of registers connection, each gentile consisting of 2 and logic elements I. The information inputs of the device are connected to the inputs of the first register, and the information outputs of the device are outputs of the first and second registers. The permitting inputs of the valves, with which the outputs of registers from the second to the penultimate last are connected to the inputs of the next in order order of increasing register numbers, are connected to the first control input of the device and through the HE element the second control input, with which the inputs of registers from the second to the last but one last are connected to the outputs of the next in order of the increasing numbers of the register, connected to the first control input through the logical element NOT, Except that, the outputs of the second register are connected vzsodami with the first register through a valve, permitting. the inputs of which are connected to the second control input and through the element NOT to the third control input and to the inputs of the last register through a gate whose inputs are connected to the first control input through the element NOT and to the second control input. The first register registers are connected to the last register outputs via an enable circuit, the gates of which are connected to the first control devices and through the element NOT to the second and third inputs. The advantage of the device is the possibility of arbitrary parallel data exchange between registers and the possibility of re-recording data stored in the first and second registers in the last register for further storage, while the block diagram is retained. The store memory device allows for different types of organization of data input and output to the memory and from the memory: Last entered - first left, First entered - first left, and First entered - last left, which is an additional advantage. The device allows the processing of arithmetic expressions whose operands are written in arbitrary order in the magazine storage device. The possibility of arbitrary. Parallel data exchange between registers. Increases the speed of many data processing algorithms recorded in a magazine storage device, which leads to a broad: application of magazine storage devices in the design of large, small and micro digital computers. Below is a block diagram of a magazine storage device. The device consists of N by -I-split registers and valves for paraphase connection of registers, each of which consists of 2 VI parallel-connected logic elements And, moreover, the enabling inputs of registers 2 from the second to the last but one are connected to the inputs of the next in order of increasing numbers numbers are connected with the first control input 3 of the device and through the elements NOT 6 with the second control input 4, and the enable input of the valves 7, with which the inputs of the registers 2, are connected from the second to the last but one to the outputs of the next in order of increasing register numbers, connected to the first control input 3 via the NOT element 6. The outputs of the second register are connected to the inputs of the backup register via the gate 8, the enabling inputs of which are connected to the second control input 4 and through the NOT element 6 to the third control The device 5 input and also with the last register inputs through the valve 9, the enabling inputs of which are connected to the first and second control inputs 3 and 4 through the element NOT b to the third control input 5. The outputs of the first register are connected to the input second register through the valve 10, the enable input of which is connected to the first control bus 3, and also to the inputs of the last register through the valve 11, the enabling inputs of which are connected to the first control input through the NOT element and the second control input 4, the inputs of the first register are connected to the outputs after the register through the valve 12, the enabling inputs of which are connected to the first control input 3 and through the NOT element to the second and third control inputs 4 and 5. The inputs 13 and 14 of the data record of the device are connected, the inputs of the first the register, and the outputs 15 and 16 of the first register, the second registers, respectively, are outputs of the data output device. Power and sync inputs are not listed.
    Store the storage device works as follows.
    When applying to the control inputs 3-5 of the control code 1 О О, the registers 2 are connected through the gates 10,, 1, 12 opened with this code so that the contents of each register are transferred cyclically to the next one in order of increasing the numbers to the register. Data fi devices. E transferred one step to the final register, and from the last to the first, i.e. the device implements a conversion
    123 .. N-1 N
    S,
    N 1 2.. . N-2N-1
    in which on the first row there are numbers of registers that receive the contents of the corresponding registers indicated on the second row of the transform.
    When control code 101 is supplied. To the inputs 3-5, the conversion is realized
    1 2 3N-1 N
    g
    1 1 2 K-2N-1
    0
    By means of which the contents of the first register are written in the second (duplicated), and the contents of the other registers are transferred one step to the last. The above two equivalent codes serve to fill the magazine storage device. When a control code O 1 O is applied to the control inputs 3-5, registers 2 are connected via gates 7, 8, 11, each register transferring its contents to the register, the number of which it precedes it, and the first register transfers to the last one, t. e. the device is transforming
    five
    Frequency converter
    41
    , N-1 N
    1 23
    .N-1; 23
    wherein the data in the device is not (transferred to its beginning for output or processing, with the contents
    The 0 of the first register is written back to the last empty register and: Can be used for further processing, if necessary. When submitting code 01 contents
    5 registers 2 are transferred cyclically from the last to the second via gates 7 and 9, and the contents of the first register are stored, i.e. conversion is implemented
    / 1 AJ.
    one)
    -il
    0
    23
    24 ....
    which is necessary when the result obtained is already in the first register as the first operand, and in the third register the second operand.
    5 At the same time, the contents of the second register are remembered again in the last register and can be used for more advanced processing. When applying the code 0 1 1 to the inputs 3-5, the transformation
    one)
    / 1 2 3.
     (l 34
    moreover, the contents of registers 2, starting with the last and ending third,
    5 is moved one step forward, and the contents of the first register are saved, and it is also recorded again in the last register. The remaining two of the control codes have
    0 has a similar purpose and is distinguished by the register number, first or second, which should fall into the last register. When submitting the code, 110 the first and second registers of exchange,
    5 is embedded in its contents, and the contents of the remaining registers are not changed, which is obtained by resolution (Diagrams 10 and 8. The transformation that is realized is
    s
    CdJinO J
    and - 1N
    2 3.ИI / 1 2 Л2. 1 il- im /
    3
    This conversion is necessary for exchanging the places of two operands when performing some arithmetic processing. Feed code combinations 000 and 111 to control inputs: disabled. A combination of control inputs 3-5, in which the contents of a register do not change, is not provided. If this is necessary, control tires
    should be able to be turned off 1 by about high impedance) or a bus should be provided enabling synchronization {synchro; . Information inputs 13: can be used to write data reads from external memory, and inputs 14 to record the results of an arithmetic unit whose inputs are connected to outputs 15 and 16. Paraphase data transfer between register 1 is necessary because during monophase communication, registers which retain their contents, will be zeroed and, in addition, the links between the registers will become more complex and the combination part will increase. Transformations, /) $, P, -t, form a basis with respect to all transformations, the sets i, 2} i.
    In this way, any exchange between the registers can be realized by submitting a suitable control word from the above codes, in which the transformation corresponding to this exchange decomposes in a certain sequence ((reproducing) basic converters 5,6, P, t, 9 In order to obtain these expansions, a digital computer is used, for which algorithms and programs exist, for example, if the number of registers is 8, to implement the transformation
    “,, / 1 2 3 45 6 7 8
    5 3 3 1 4 5 6 78 /
    a control word 110, 010,110,101 is needed because the decomposition of the transformation in the basis, Pit-, V, g 8 is I.t, c, t. ,
    The multiplication in the decomposed transform is performed from left to right, and the control word is formed using the appropriate base transform codes in reverse order. Conversion, for example, is necessary if it is necessary to obtain 1 square of the third register (by feeding the contents of the first and second 0 registers to the arithmetic unit), and add the result to the contents of the first register, with the following operations using the contents of the following registers in the order of their numbers without changes.
    权利要求:
    Claims (3)
    [1]
    STORING MEMORY DEVICE, consisting of series-connected registers in the direction from the first to the last and vice versa through resolving circuits for paraphase communication between the registers, each of which consists of -2 η parallel-connected logic elements And, where and is the bit depth of the registers, while the information the inputs of the device are connected to the inputs of the first register, and the outputs of the first and second registers are the information outputs of the device, characterized in that the enable inputs of the enable circuits are 1 hour cut outs which registers
    [2]
    2, from the second to the last but one, are connected to the inputs of the next highest register numbers, connected to the first control input '3 and through the logic element NOT (6 with the second control input 4 devices, and the enable inputs of the enable circuits 7, through which the inputs of the registers 2 from the second to the penultimate one, they are connected to the outputs of the next higher order of the register numbers, connected to the first equalizing input 3 through the element NOT 6, while the outputs of the second register are connected through a permissive circuit 8, whose permissible inputs are connected us with a second control input 4 and 6 through the NOT element - to a third control input 5, the first register and outputs through the resolving circuit 9 permitting inputs from Torah Ko associated with a first and second yn <g equals inputs 3 and 4 and through element NOT 6 - with the third control input 5, with the inputs of the last register, and the outputs of the first register are connected to the inputs of the second through the enable circuit 10, the permitting input of which is connected with the first control input 3 and c. the inputs of the last register, and through the enable circuit 11, the enable inputs of which are connected to the first control input.
    [3]
    3 through the element NOT 6 and with the second control input, while the inputs of the first register are connected to the outputs of the latter through the enable circuit 12, the permitting inputs of which are connected to the first control input 3 and through the element NOT 6 with the second and third control inputs 4 and 5.
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    同族专利:
    公开号 | 公开日
    DK433679A|1980-05-09|
    DE2945160A1|1980-07-10|
    US4305138A|1981-12-08|
    GB2035637A|1980-06-18|
    GB2035637B|1983-03-23|
    FR2441239B3|1981-08-14|
    FR2441239A1|1980-06-06|
    BG29114A1|1980-09-15|
    JPS5567983A|1980-05-22|
    NL7907962A|1980-05-12|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    JPS5130978B1|1971-03-05|1976-09-03|GB2089536B|1980-12-12|1984-05-23|Burroughs Corp|Improvement in or relating to wafer scale integrated circuits|
    US4504925A|1982-01-18|1985-03-12|M/A-Com Linkabit, Inc.|Self-shifting LIFO stack|
    US5038277A|1983-11-07|1991-08-06|Digital Equipment Corporation|Adjustable buffer for data communications in a data processing system|
    US4813015A|1986-03-12|1989-03-14|Advanced Micro Devices, Inc.|Fracturable x-y storage array using a ram cell with bidirectional shift|
    US4864544A|1986-03-12|1989-09-05|Advanced Micro Devices, Inc.|A Ram cell having means for controlling a bidirectional shift|
    US5649150A|1995-04-12|1997-07-15|International Business Machines Corporation|Scannable last-in-first-out register stack|
    法律状态:
    优先权:
    申请号 | 申请日 | 专利标题
    BG7841323A|BG29114A1|1978-11-08|1978-11-08|Stack memory device|
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